1. Field of the Invention
The present invention is directed to methods and devices for controlling double data rate (DDR) synchronous dynamic random access memories (SDRAM). More specifically, but without limitation thereto, the present invention is directed to a controller for DDR SDRAM that provides an optional interface to intelligent requestors.
2. Description of the Prior Art
DDR SDRAM offers a straightforward and low cost approach to doubling the bandwidth of memory compared to the single data rate SDRAM currently in widespread use. The term “double data rate” means that the peak data rate is twice the rate at which commands may be clocked into the device. Specifically, commands are received as input on the positive edges of the memory clock, while the data is read or written on both the positive and negative edges of the memory clock. By doubling the transfer rate on the data bus while leaving unchanged the transfer rate of the more heavily loaded command and address bus, the far more costly alternative of doubling the memory bandwidth may be avoided.